1. Technical Field
This disclosure relates to semiconductor layouts and more particularly, to a layout for reducing interaction between storage nodes and transistors in semiconductor memory cells.
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells with storage nodes. Generally these storage nodes are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charge to be stored in the storage node or retrieves charge from the storage depending on whether the desired action is a read or write function.
In buried strap type trench capacitors, dopant outdiffusion close to a wordline can cause problems such as short channel effects in the access transistor channel.
Referring to FIG. 1, a layout is shown for conventional deep trench capacitors. Deep trench capacitors 10 are disposed under passing wordlines 12. Access transistors 14 are electrically coupled to storage nodes 16 of trench capacitors 10 through diffusion regions 18 which may be either a source or a drain of access transistors 14. Diffusion regions 20 are also included which are electrically connected to contacts 22. Contacts 22 connect to bitline (not shown) to read and write to storage nodes 16 through access transistors 14. Access transistors 14 are activated by wordlines 12. When voltage is applied to wordlines 12 a channel below wordline 12 conducts allowing current to flow between diffusion regions 18 and 20 and into or out of storage node 16.
Wordlines 12 are preferably spaced across the smallest possible distance d to conserve layout area. The smallest possible distance is typically a minimum feature size F which is achievable by the technology.
Referring now to FIG. 2 a cross-sectional view of the layout of FIG. 1 is shown. Elements of FIG. 2 are labeled as described in FIG. 1. Storage nodes 16 are isolated from a doped well 24 by a dielectric collar 26. Shallow trench isolation 28 is provided over storage nodes 16 to electrically isolate the passing wordlines 12 formed above storage nodes 16. Diffusion regions 18 of access transistors 14 are connected to storage node 16 by a node diffusion region 30 to a buried strap 32. Node diffusion 30 and buried strap 32 are typically connected by outdiffusing dopants which mix to create a conductive region (node region 30) therebetween.
In a conventional layout, the distance between wordlines 12 and buried strap 32 is usually 1F. But, if the overlay tolerance is considered, the dopant outdiffusion from buried strap 32 can potentially outdiffuse far enough to interact with a channel 34 below a gate 36 (wordline 12) causing short channel effects in access transistor 14. In typical layouts, an overlay tolerance is F/2, i.e., a worst case distance is F/2. A length of channel 34 is a function of diffusion regions 18 and 20 and buried strap 32 outdiffusion. Also, it is a function of the overlay tolerance between wordlines 12 and deep trenches 10. If the dopant outdiffusion length form buried strap 32 is larger than F/2, the length of channel 34 becomes less than 1F. However, outdiffusion form buried strap 32 must generally be far enough (about F/2) to form a connection between diffusion region 18 and buried strap 32.
As shown in phantom lines in FIG. 2, a worst case of misalignment between trench 10' and wordline 12 is shown. Further outdiffusion from buried strap 32' is such that channel length of channel 34 is reduced thereby causing short channel effects in access transistor 14.
Therefore, a need exists for a layout for semiconductor memories which reduces interaction between a buried strap and an access transistor channel.